1. Field of the Invention
The present invention relates to production of a semiconductor device and, in particular, to an aqueous polishing liquid in a wiring step for a semiconductor device and a chemical mechanical polishing method employing same.
2. Description of the Related Art
With regard to the development of semiconductor devices represented by large-scale integrated circuits (hereinafter, denoted by ‘LSI’), in order to achieve small dimensions and high speed there has in recent years been a demand for higher density and higher integration by increasing the fineness and the layering of wiring. As techniques therefor, various techniques such as chemical mechanical polishing (hereinafter, denoted by ‘CMP’) have been employed. CMP is an essential technique for carrying out surface planarization of a film that is to be processed such as an interlayer insulating film, plug formation, formation of embedded metal wiring, etc., and carries out removal of a surplus metal thin film during the planarization of a substrate or the formation of wiring. This technique is disclosed in, for example, U.S. Pat. No. 4,944,836.
A general CMP method involves affixing a polishing pad to a circular polishing platen, soaking the surface of the polishing pad with a polishing liquid, pressing the surface of a substrate (wafer) against the pad, and rotating both the polishing platen and the substrate while applying a predetermined pressure (polishing pressure) to the reverse sides thereof, thus planarizing the surface of the substrate by means of the mechanical friction generated.
The polishing liquid used in CMP generally comprises abrasive grains (e.g. alumina, silica) and an oxidizing agent (e.g. hydrogen peroxide, persulfuric acid). It is surmised that the basic mechanism involves oxidizing the metal surface by the oxidizing agent and polishing by removing the oxidized film by means of the abrasive grains, and it is described in, for example, Journal of Electrochemical Society, 1991, Vol. 138, No. 11, p. 3460 to p. 3464.
However, when CMP is carried out using a polishing liquid comprising such solid abrasive grains, abrasive damage (scratching), a phenomenon in which the entire surface to be polished is abraded more than necessary (thinning), a phenomenon in which the metal surface to be polished bends in a dish shape (dishing), a phenomenon in which an insulator between metal wires is abraded more than necessary and a plurality of metal wiring surfaces bend in a dish shape (erosion), etc. might occur.
Furthermore, in a washing step, which is normally carried out after polishing in order to remove polishing liquid remaining on the semiconductor surface, due to the use of the polishing liquid comprising the solid abrasive grains the washing step becomes complicated, and when disposing of the liquid after washing (liquid waste) it is necessary to separate the solid abrasive grains by sedimentation, which causes a problem in terms of cost.
As means for solving these problems, for example, a metal surface polishing method involving combination of dry etching and a polishing liquid containing no abrasive grains is disclosed in Journal of Electrochemical Society, 2000, Vol. 147, No. 10, p. 3907 to p. 3913, and a polishing liquid comprising hydrogen peroxide/malic acid/benzotriazole/ammonium polyacrylate and water is disclosed in JP-A-2001-127019 (JP-A denotes a Japanese unexamined patent application publication). In accordance with these methods, a metal film on a projecting portion of a semiconductor substrate is selectively subjected to CMP, the metal film in a recessed portion remains, and a desired conductor pattern is thus obtained. Since CMP proceeds due to friction with a polishing pad that is mechanically much softer than the conventional solid abrasive grains, the occurrence of scratches is suppressed. However, there is the defect that, due to a decrease in the physical polishing force, a sufficient polishing rate cannot be obtained.
On the other hand, as metals for wiring, tungsten and aluminum have been commonly used in an interconnect structure. However, with the aim of achieving higher performance, an LSI employing copper, which has a lower wiring resistance than that of the above metals, has been developed. As a method for wiring with copper, a damascene method is known from, for example, JP-A-2-278822. Furthermore, a dual damascene method in which a contact hole and a wiring trench are simultaneously formed in an interlayer insulating film, and a metal is embedded in the two has been widely used. As a target material for copper wiring, a copper target having a high purity of five nines or greater has been shipped. However, due to a recent increase in the fineness of wiring for the purpose of achieving higher density, it is necessary to improve the conductivity and electronic characteristics of copper wiring, and accompanying the above, the use of a copper alloy formed by adding a third component to high purity copper has been examined. At the same time, there is a desire for high speed metal polishing means that enables high productivity to be exhibited without contaminating these high definition, high purity materials. When polishing copper metal, since it is a particularly soft metal, the above-mentioned dishing, erosion, or scratching easily occurs, and a polishing technique with higher precision has been desired.
Moreover, in order to improve the productivity, the diameter of a wafer when producing an LSI has been increasing in recent years; currently, one with a diameter of 200 mm or greater is commonly used, and production employing one with a diameter of 300 mm or greater has also started. Accompanying this increase in wafer dimensions, a difference in polishing rate between the central area and the peripheral area of the wafer easily occurs, and there is an increasing desire for the polishing in the plane of the wafer to be uniform.
As a chemical polishing method employing no mechanical polishing means for copper and a copper alloy, a method described in JP-A-49-122432 is known. However, a chemical polishing method employing only a chemical dissolution action still has a serious problem with the planarity since, compared with CMP, in which a metal film on a projection is selectively polished chemically and mechanically, a recess is scraped out, that is, dishing, etc. occurs.
Furthermore, in order to prevent copper ions from diffusing into an insulating material when copper wiring is employees, a diffusion-preventing layer, which is called a barrier layer, is generally provided between a wiring section and an insulating layer, as a single layer or two or more layers selected from TaN, TaSiN, Ta, TiN, Ti, Nb, W, WN, Co, Zr, ZrN, and a CuTa alloy. However, since these barrier materials themselves have conductive properties, it is necessary to completely remove the barrier material on the insulating layer in order to prevent the occurrence of errors such as leakage current, and this removal process is carried out by a method similar to bulk polishing of a metal wiring material (barrier CMP). When carrying out bulk polishing of copper, since dishing easily occurs particularly in a wide metal wiring section, in order to achieve final planarization it is desirable that the amount removed by polishing can be adjusted between the wiring section and the barrier section. Because of this, it is desirable that a polishing liquid for barrier polishing has an optimum polishing selectivity between copper and the barrier metal. Moreover, since the wiring pitch and the wiring density are different in each wiring layer level, it is more desirable that the above-mentioned polishing selectivity can be appropriately adjusted.